OPS-SAT@Imperial testing commercial FPGAs in space
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The Ideal on board Processor

Written by Shane Fleming

a misunderstood AI perhaps?

What would the ideal on board spacecraft processor look like? Me and my colleague Felix Winterstein feel that it would have the following properties:

  • High Processing Power
  • Low power/energy consumption
  • Flexibility to change things “in orbit”
  • Rad-hard

The ideal satellite processor would have high processing power… High processing power is desirable in space applications but is often difficult to achieve. One example is compression algorithms, these computationally intensive algorithms are useful as they reduce the amount of downlinking required (transmission back to earth) . Such high processing power comes at a cost though, as fast CPUs generally use a lot of power and energy, taking us to our next point.

The ideal satellite processor would have low power consumption… Power consumption and energy usage are huge constraints in satellite designs, generally because everything needs to be powered from small solar panels. The output from the solar panels is often not reliable; a tumbling satellite might not get full exposure to the sun, and power production degrades over time due to exposure to radiation. This often requires a great deal of power “slack” further reducing the power/energy available for processing.

The ideal satellite processor would be flexible… Low Earth Orbit is a pretty difficult place to reach, and when designing big complex systems mistakes happen and situations change. In this regard software is great because it is flexible, patches/fixes can be tested on the ground and applied to the craft remotely. However hardware is inflexible, for example if a silicon bug causes an interrupt to occur with an incorrect priority then it might not be detected during ground testing but could cause uncorrectable problems in orbit.

The ideal satellite processor would be Rad-Hard… Rad-Hard refers to radiation hardened, but is becoming a more general term for reliable, fault tolerant, electronics. Radiation is a problem for on board computers as unwanted energy can cause memory bits to flip from 1 to 0, or 0 to 1. This radiation is usually in the form of high energy energy ionizing particles that are caught in the earths magnetic field or emitted during high energy events such as a coronal mass ejection from the Sun. Memory circuits, such as SRAM cells, are particularity sensitive to faults from this type of radiation and for this reason cache memories are often heavily rad protected in space computers.

an FPGA!

One of the goals of the OPS-SAT experiment is to investigate how commercial FPGAs (ones that are not specifically designed for space) can be used to perform onboard computation. So a good question is, how do FPGAs compare against the ideal spacecraft processor?

  • FPGAs have high processing power - True for certain applications. They are great at parallel processing, this makes them great for applications like medical imaging or digital signal processing.

  • FPGAs have low power/energy consumption - True in fact microsoft have been using FPGAs in their Bing search engine for this very reason.

  • FPGAs are flexible - True Once deployed FPGAs can be reprogrammed to perform a completely different task. Within a few hundred milliseconds they can be changed from a multicore processor to an application specific image processing unit. (They even have “field programmable” in their name)

  • FPGAs are Rad-Hard - False FPGA circuits are described in memory (SRAM) which is sensitive to bit flips caused by high energy particles. Bit flips caused by these particles could alter the data the FPGA is processing, or worse still, reconfigure the actual structure of the circuit altering logic gates from one type to another or by altering how components are connected together.

Our work (documented in this blog) aims to investigate how sensitive these commercial FPGAs are to bit flips in orbit and methods for protecting them, bringing FPGAs closer to the ideal onboard processor.

The arrival of the MityARM at Imperial

Written by Shane Fleming

The MityARM development board

Despite OPS-SAT being a CubeSat, weighing in at only 6Kg, its computational ability will be more than ten times anything currently in the European Space Agencies fleet. One of the computational units, which just got delivered to our research group, can be seen in the picture above. This is a critical links MityARM SoC (system on chip) development board, and is one of four that will make up OPS-SATs computation payload.

One of the reason that this mission will be computationally more powerful than any other is because it is using commercial off the shelf components (COTS). This means that instead of components being custom made (the usual approach in satellite design) general purpose ones were bought. COTS dramatically reduce the costs but there is one major issue in using them, radiation.

High energy particles emitted from the sun and/or trapped in the Earths magnetic field can disrupt electronics in orbit. When one of these particles strikes a device it can cause what is known as a Single Event Upset (SEU), flipping a bit from a 1 to a 0, or 0 to a 1. This unintended change in state can have catastrophic consequences, for example the TDRS-1 communication satellite experienced SEUs in its Attitude Control System (ACS), luckily ground control was able to prevent the satellite from tumbling and maintain its proper attitude.

The MityARM SoCs in OPS-SATs payload are particularity vulnerable to the effect of high energy particles because they contain an electronic device known as an FPGA (Field Programmable Gate Array). Think of an FPGA as a blank digital circuit that you can reprogram, sort of like a “soft” digital circuit, where the description of this circuit is held in an SRAM. SRAMs are highly sensitive to SEUs and in an FPGA any bit flip can not only alter data but alter the structure of the soft circuit.

Our work aims to explore just how sensitive these modern COTS FPGAs are to high energy particles in orbit. Through building test circuits and monitoring the systems behaviour we hope to be able to provide a comprehensive data set for future space FPGA designers to use.